1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a recessed-gate thin-film transistor (RG-TFT) having a self-aligned lightly doped drain (LDD).
2. Description of the Related Art
The integration of complex circuit functions such as drivers, serial-parallel converters, video decoders, and the like on the glass panels used for LCD displays requires very high performance TFT transistors. These TFTs must operate at supply voltages of 5 V and below, to increase operating speed and decrease power consumption. MOSFET transistor performance is expressed in terms of switching speed or gate delay, and performance can be increased by decreasing operating voltage, gate oxide thickness, or channel length (Leff), increasing transistor drive current while decreasing the parasitic capacitances associated with the transistor structure. Devices with performance sufficient to meet the needs of advanced circuits operating at 5 V typically have gate lengths less than 1 micrometer (um) and gate oxide thickness below 15 nanometers (nm). An important side effect of decreasing transistor gate length and gate oxide thickness is the increase in field strength that occurs at the edge of the gate electrode adjacent to the drain. This increased field leads to several undesirable effects such as Vt roll-off, hot carrier injection, and drain induced barrier lowering (DIBL), which are generally referred to as short channel effects or SCE. An additional unfavorable effect that is applicable to fully depleted SOI and thin film transistors is the kink effect which causes high current instability for NMOS transistors.
FIG. 1 is a cross-sectional view of a TFT and a graph of current v. voltage (I-V) illustrating the kink effect at a high drain voltage (prior art). The kink effect is caused by the following chain of events. A high field is generated at the gate—drain edge, due to the applied voltages Vd and Vg, causing hot carrier injection, which in turn, generates electron-hole pairs. The field between source and drain moves holes to the source junction where they are trapped between the source junction and the substrate. The pile up of holes leads to a decrease in potential at the source edge of the gate, which has the effect of decreasing the channel length and increasing current. If the effect is severe, this current increase can lead to thermal cascade, melting, and failure of the device.
FIG. 2 is a partial cross-section of a TFT device and a simulation of the magnitude of the electric field under the gate for different device architectures (prior art). One widely-used strategy for improving short channel effects is to use lower doping at the edge of the MOSFET gate, as compared to the source/drain doping, in order to decrease the magnitude of the maximum field. Simulations of three approaches (Double Diffused Drain, Lightly Doped Drain, and gate overlapping Drain) are shown (from R. Izawa et al., “Impact of the Gate-Drain Overlapped Devices (GOLD) for Deep Submicrometer VLSI”, IEEE Trans. Electron Devices 35, 2088 1988). The Double Diffused Drain architecture is not appropriate for liquid crystal display (LCD) fabrication because the process flow requires a very high temperature anneal to diffuse arsenic and phosphorus dopants at different rates. Both the LDD and GOLD architectures have been used for fabrication of TFT devices on glass substrates, and they are described briefly below.
FIG. 3 shows partial cross-sectional views of a transistor, depicting steps in the fabrication of an LDD structure formed with spacers (prior art). The use of a Lightly Doped Drain (LDD) structure to decrease the field intensity at the edge of the gate and improve short channel effects is well known in conventional CMOS processing. A schematic summary of the process of forming a device with an LDD structure is shown. Briefly, the process flow is as follows. After patterning the gate electrode, a low dose N or P type implant forms the LDD region. The implant density is typically about 1 to 3e13 cm−2, and the dopant is self-aligned with the gate electrode. A dielectric such as SiO2 or a composite layer of SiO2 and Si3N4 is deposited as a conformal layer over the gate and etched anisotropically to form spacers. The source and drain regions are doped with a high dose N or P type implant (typically implant density is about 1 to 7e15 cm−2), and the spacers protect the LDD region from the source/drain implant. In this case, the width of the LDD region is determined by the spacer width.
Thus, the LDD region has a higher resistance than the source/drain regions, and the voltage drop between drain and gate is spread over a larger distance than it would be if the junction between drain and channel regions were abrupt. In this way, the maximum field is decreased and short channel effects are decreased. Other methods are also known for forming lateral offsets between LDD and S/D implant.
FIG. 4 shows partial cross-sectional views of a transistor, depicting steps in the fabrication of a TFT using a GOLD process (prior art). A technique similar to the LDD approach, which has been used on TFT devices with long channels, is the Gate-Overlapping-Drain or GOLD process, which uses a medium dose implant prior to gate deposition to form a lightly doped drain region under the gate edge. Briefly, the process flow is as follows. Photoresist is patterned to protect the active silicon layer where the transistor channel is to be formed. An ion implant with a low dose of N (for NMOS transistor) or P (for PMOS transistor) type dopant forms the GOLD region. The implant density is typically about 1 to 9e13 cm−2. The position of the photoresist pattern with respect to the gate electrode determines the GOLD region width, so the GOLD process is not self-aligned. The gate dielectric (typically CVD SiO2) is deposited followed by the gate electrode, which may be doped polysilicon or a metal such as WTa, and the gate is patterned. The source and drain regions are doped with a high dose N or P type implant (typically implant density is about 1 to 7e15 cm−2). The gate electrode protects the GOLD region from the source/drain implant, so the width of the GOLD region is determined by the overlap between the gate edge and the GOLD implant edge.
All of the LDD formation techniques based on the use of a spacer suffer from variations in dopant due to the changes in thickness and step coverage of the spacer layer, and especially in the amount of over etch and the degree of isotropic etching in the spacer etch. In addition, the width of the spacer is limited to being less than the height of the gate stack used to form the edge of the spacer. If a wider spacer is required for high voltage devices, it is not practical to increase the gate electrode thickness.
The GOLD technique is limited by the resolution of lithography used for LCD panel fabrication and by the amount of overlay matching between the GOLD photo pattern and the gate patterning. For current fabrication methods the resolution limits for a step is about 1 um. Overlay matching, particularly across the very large glass substrates used for LCD panel fabrication, is very difficult and the variation in GOLD width due to differences in placement between the gate and GOLD layers may be as much as 1 um. As a consequence, the GOLD technique can only be used for long channel devices with gate lengths of about 4 um. The GOLD technique is not suitable for controlling SCE in high performance devices with sub-micron gate lengths.
It would be advantageous if a device structure and corresponding process existed for producing an LDD region with a well controlled LDD width in a single ion doping step, self-aligned to the gate, and suitable for sub-micron gate lengths.